In recent years, non-volatile memories that can retain data even when the power is switched off are widely used. In flash memories that are typical non-volatile memories, the transistors forming the memory cells have floating gates or insulation films that are known as charge storage layers. In such flash memories, charges are accumulated in the charge storage layers, so as to store data. An example of a flash memory having insulating films as charge storage layers is a flash memory with a SONOS (Silicon Oxide Nitride Oxide Silicon) structure that stores charges in the trapping layer of an ONO (Oxide/Nitride/Oxide) film. U.S. Pat. No. 6,011,725 discloses a SONOS flash memory (a conventional example 1) that has virtual-ground memory cells each replacing the source and drain with each other, and operating the source and drain in a symmetrical fashion. In the conventional example 1, the source and the drain are replaced with each other, and are operated in a symmetrical fashion, so that two charge storage regions can be formed in the charge storage layer between the source and drain in a single transistor. Accordingly, 2-bit data can be stored in each one transistor.
In the conventional example 1, however, the channel length becomes smaller as the memory cells are made smaller, and it becomes difficult to separate the two charge storage regions from each other in the charge storage layer between the source and drain. As a result, it becomes difficult to write charges in one charge storage region independently of the other charge storage region. To counter this problem, Japanese Unexamined Patent Publication No. 2005-517301 discloses a flash memory (a conventional example 2) that can have smaller memory cells. FIG. 1 is a cross-sectional view of the flash memory of the conventional example 2. As shown in FIG. 1, a groove 30 is formed in a semiconductor substrate 10, and an ONO film 20 formed with a bottom oxide film 14, trapping layer 16 as charge storage layers, and a top oxide film 18 is provided on both side faces of the groove 30. A word line 24 that also serves as a gate electrode is provided on the top oxide film 18. Bit lines 12 that also serve as a source and drain are provided on both sides of the groove 30 and in the semiconductor substrate 10.
In the conventional example 2, even if the distance between the bit lines 12 becomes shorter, a channel 51 having a channel length around the groove 30 is formed. Accordingly, a longer channel length can be obtained. In this manner, two charge storage layers that are separated from each other can be formed between the source and drain. Also, the trapping layers 16 are not formed on the bottom face of the groove 30, and include a right layer and a left layer. Thus, higher separability in writing charges into the left and right trapping layers is achieved.
In the conventional example 2, however, it is difficult to read the data stored in one trapping layer 16 independently of the other trapping layer 16 (or to determine whether charges are accumulated in the left and right trapping layers 16). Referring to FIG. 1, this problem is explained. Reading data from the left trapping layer 16 is performed as follows. The bit line 12 on the left side is the source, and the bit line 12 on the right side is the drain. When electrons are accumulated in the left trapping layer 16, the current flowing through the channel 51 between the source and drain becomes lower due to the electric field of the trapping layer 16. When no charges (electrons) are accumulated in the left trapping layer 16, the current flowing through the channel 51 becomes higher. By detecting the current, the data in the trapping layers 16 is read out.
However, as indicated by the arrow 50 in FIG. 1, the electric field formed by the charges in the right trapping layer 16 passes through the bottom oxide film 14 and the top oxide film 18 on the bottom face of the groove 30, and reaches the channel 51 in the vicinity of the left trapping layer 16. When the data stored in the left trapping layer 16 is read out, the current flowing through the channel 51 is affected by the charges accumulated in the right trapping layer 16. As a result, separate data reading becomes difficult.